1. Field of the Invention
The present invention relates to thin film magnetic memory devices, and more particularly to a thin film magnetic memory device provided with a redundant configuration.
2. Description of the Background Art
A magnetic random access memory (MRAM) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device stores data in a non-volatile manner using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit, and permits random access to the respective thin film magnetic element.
In particular, it has recently been reported that provision of thin film magnetic elements having magnetic tunnel junctions (MTJ) as memory cells significantly improves the performance of the MRAM device. The MRAM device provided with such memory cells having magnetic tunnel junctions is disclosed in technical documents such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000, and “A 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 17 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as the “MTJ memory cell”).
Referring to FIG. 17, the MTJ memory cell includes a tunneling magneto-resistance element TMR having its electric resistance changing according to a level of stored data, and an access element ATR for forming a path of a sense current Is passing through tunneling magneto-resistance element TMR at the time of data read. Hereinafter, access element ATR is also referred to as an access transistor ATR, since it is typically formed of a field effect transistor. Access transistor ATR is coupled between tunneling magneto-resistance element TMR and a fixed voltage (ground voltage Vss).
A write word line WWL for designating data write, a read word line RWL for executing data read, and a bit line BL as a data line for transmitting an electric signal corresponding to a level of stored data at the time of the data read and the data write, are arranged for the MTJ memory cell.
FIG. 18 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.
Referring to FIG. 18, tunneling magneto-resistance element TMR has a ferromagnetic layer (hereinafter, also simply referred to as the “fixed magnetic layer”) FL having a fixed, constant direction of magnetization, and a ferromagnetic layer (hereinafter, also simply referred to as the “free magnetic layer”) VL magnetized in a direction corresponding to the magnetic field externally applied. A tunneling barrier (tunneling film) TB formed of an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in a direction the same as or opposite to fixed magnetic layer FL in accordance with the level of the stored data to be written. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
At the time of data read, access transistor ATR turns on in response to activation of read word line RWL. This allows a sense current Is to flow through a current path from bit line BL via tunneling magneto-resistance element TMR and access transistor ATR to ground voltage Vss.
The electric resistance of tunneling magneto-resistance element TMR changes in accordance with the relative relation between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, when the magnetization direction of fixed magnetic layer FL and the magnetization direction of free magnetic layer VL are the same (parallel), the electric resistance of tunneling magneto-resistance element TMR becomes small compared to the case where the two layers have opposite (anti-parallel) magnetization directions.
Thus, when free magnetic layer VL is magnetized in a direction according to the stored data, voltage change occurring in tunneling magneto-resistance element TMR due to sense current Is will differ in accordance with the level of the stored data. Accordingly, if sense current Is is passed through tunneling magneto-resistance element TMR after precharging of bit line BL to a certain voltage, for example, then the stored data in a MTJ memory cell can be read by sensing the voltage of bit line BL.
FIG. 19 is a conceptual diagram illustrating a data write operation to the MTJ memory cell.
Referring to FIG. 19, at the time of data write, read word line RWL is inactivated, and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL to a direction in accordance with the write data is passed through write word line WWL and through bit line BL. The magnetization direction of free magnetic layer VL is determined by the data write currents flowing through the respective lines of write word line WWL and bit line BL.
FIG. 20 is a conceptual diagram illustrating a relation between the data write current at the time of data write to the MTJ memory cell and the magnetization direction of the tunneling magneto-resistance element.
Referring to FIG. 20, the horizontal axis H (EA) represents the magnetic field applied to free magnetic layer VL within tunneling magneto-resistance element TMR in an easy-to-magnetize, or, easy axis (EA) direction. The vertical axis H (HA) represents the magnetic field acting on free magnetic layer VL in a hard-to-magnetize, or, hard axis (HA) direction. Magnetic fields H (EA) and H (HA) correspond respectively to two magnetic fields generated by the currents flowing through bit line BL and write word line WWL.
In the MTJ memory cell, the fixed magnetization direction of fixed magnetic layer FL is along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized in the parallel (same) or anti-parallel (opposite) direction with respect to fixed magnetic layer FL along the easy axis direction, in accordance with the level (“1” or “0”) of the stored data. Hereinafter, the electric resistances of tunneling magneto-resistance element TMR corresponding to the two magnetization directions of free magnetic layer VL will be referred to as R1 and R0 (R1>R0). The MTJ memory cell can store data of one bit (“1” or “0”) corresponding to respective one of the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only in the case where the sum of applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in FIG. 20. In other words, the magnetization direction of free magnetic layer VL would not change if the applied data write magnetic field has an intensity corresponding to the region inside the asteroid characteristic line.
As seen from the asteroid characteristic line, a magnetization threshold value necessary to change the magnetization direction along the easy axis can be lowered by applying to free magnetic layer VL the magnetic field in the hard axis direction.
Assume that operating points at the time of data write are designed as in the example shown in FIG. 20. In this case, in the MTJ memory cell to which data is to be written, the data write magnetic field in the easy axis direction is designed to have an intensity of HWR. In other words, the value of the data write current to be passed through bit line BL or write word line WWL is designed such that the relevant data write magnetic field HWR is obtained. In general, data write magnetic field HWR is expressed by the sum of a switching magnetic field HSW necessary to switch the magnetization direction and a margin ΔH: HWR=HSW+ΔH.
To rewrite the stored data of the MTJ memory cell, or, the magnetization direction of tunneling magneto-resistance element TMR, a data write current of at least a prescribed level should be passed through both write word line WWL and bit line BL. By doing so, free magnetic layer VL in tunneling magneto-resistance element TMR can be magnetized in the same (parallel) or opposite (anti-parallel) direction with respect to fixed magnetic layer FL, in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetization direction once written into tunneling magneto-resistance element, i.e., the stored data of the MTJ memory cell, is held in a non-volatile manner until new data is written.
As such, the electric resistance of tunneling magneto-resistance element TMR changes according to the magnetization direction that is rewritable with the data write magnetic field being applied. Thus, by making the two magnetization directions of free magnetic layer VL in tunneling magneto-resistance element TMR correspond to the levels (“1” and “0”) of the stored data, the data can be stored in a non-volatile manner.
In the MRAM device, data is read utilizing an electric resistance difference ΔR=(Rmax−Rmin) that is a junction resistance difference in tunneling magneto-resistance element TMR corresponding to the difference of the stored data levels. In other words, data read is performed by sensing a current passing through a selected memory cell, i.e., sense current Is.
Generally, in addition to the normal MTJ memory cells for use in data storage, dummy memory cells are provided for comparison with the selected memory cell. The dummy memory cells need to be fabricated such that they each have an electric resistance of an intermediate level between the two electric resistances Rmax and Rmin corresponding to the stored data levels of the MTJ memory cell. Implementation of such an electric resistance requires special design and fabrication of the dummy memory cells. If the dummy memory cells do not have electric resistance values as designed, data read margin would be impaired.
Further, generally in a memory device, in addition to provision of a plurality of normal memory cells being selected with address signals, a redundant configuration for repair of defects in the normal memory cells is provided to improve manufacturing yield. In the redundant configuration, replacement/repair of the defective memory cells is conducted in units of sections, using spare memory cells additionally provided.
In the redundant configuration in the MRAM device, it is necessary to make it possible to replace/repair not only the normal MTJ memory cells but also the dummy memory cells. In other words, the spare memory cells should be arranged efficiently, taking account of replacement of the dummy memory cells as well as the normal memory cells.